1. Field of the Invention
The present invention relates to an option setting circuit for use in a one-chip microcomputer employed in an electronic apparatus, such as a camera, a compact disk player and a video cassette recorder, provided with a one-chip microcomputer.
2. Description of the Prior Art
Conventionally, an interface circuit, such as a one-chip microcomputer, is provided with an option setting circuit since options may be changed after the manufacture in accordance with the structures of peripheral integrated circuits (ICs) and discrete parts. Such an option setting circuit is also used to change options on the spot when specifications are changed while a system is being designed in an IC chip for evaluating an application program for a one-chip microcomputer.
FIG. 1 shows a conventional option setting circuit. An input/output (I/O) circuit 1 is provided with an inverter 2 and a p-channel metal oxide semiconductor (MOS) transistor 4 for pulling up an input terminal of the inverter 2 to a power supply line 3. When an input terminal of the inverter 2 is connected through an input pad 5 to, for example, an external switching circuit, if the switching circuit is a complementary metal oxide semiconductor (CMOS) transistor, since both "0" and "1" signals are produced in the switching circuit and are input to the input pad 5, it is unnecessary to pull up the input terminal of the inverter 2 to the power supply line 3. Hence, the transistor 4 is set to be disabled.
However, when the external switching circuit is constituted by, for example, an n-channel MOS transistor which is connected between the pad 5 and a ground line, since only a "0" signal is input to the input pad 5, it is necessary to produce a "1" signal in the I/O circuit 1. Hence, in that case, it is necessary to design the option setting circuit so that the transistor 4 is always ON. Under a condition where the transistor 4 is ON, the input of the inverter 2 is "1" (a voltage VDD at the power supply line 3) when the external switching circuit is OFF, while the input of the inverter 2 is "0" when the external switching circuit is ON since a "0" signal is input. In FIG. 1, 6 is a resistor, and 7 is a protecting circuit including diodes D1 and D2.
The setting of whether to activate or disable the transistor 4 (option setting) is performed as follows. An option data read only memory (ROM) 11 (e.g. an electrically erasable programmable read only memory [EEPROM]) and an option latch circuit 8 are simultaneously opened when the data on an address data bus line 9 is changed to an option address data specifying the present option latch circuit 8, and an option data is read out from an address of the option data ROM 11 which is specified by the option address data. A specified option latch circuit 8 takes in the option data through a data bus line 10.
In this case, the data output from the option data ROM 11 is "1" or "0". For example, when a "0" signal is output and is latched by the option latch circuit 8, the output of the option latch circuit 8 is "0", i.e. low, so that the transistor is activated.
Then, when the data on the address data bus line 9 is changed to another address data not specifying the present option latch circuit 8, the option data ROM 11 and the option latch circuit 8 are both closed, so that data transfer is stopped. Thus, the option setting is completed.
The data on the address data bus line 9 is changed to the option address data specifying the present option latch circuit 8 during an option setting period at the time of resetting. If an external reset signal is applied, for example, by a depression of a reset button in the case of the personal computer, during the operation period of the one-chip microcomputer (i.e. during the program running period) after the turning on of the power, first and second internal reset signals (being active under high state as shown at (b) and (c) in FIG. 2) which extend the reset period are produced in response to the external reset signal (being active under low state as shown at (a) in FIG. 2). A non-illustrated central processing unit (CPU) of the one-chip microcomputer outputs the option address data to the address data bus line 9 during the option setting period ranging from the fall of the first internal reset signal to the fall of the second internal reset signal, so that the option is set.
The first internal reset signal is for resetting the option latch circuit 8 to its initial state. The second internal reset signal is for resetting counters and registers not associated with the option setting to their initial states. The first internal reset signal is input through inverters 12 and 13 to a set terminal S of the option latch circuit 8. In this case, an output terminal Q thereof is set to be high.
The ROM address of the option data ROM 11 is as shown in FIG. 3. That is, an option setting data ROM area 15 is allotted to an area extending from a program data ROM area 14. If the option setting data ROM area 15 begins at address 2000 and the option data at the address is for option setting for the I/O circuit 1, option setting for another I/O circuit (not shown) is performed based on, for example, an option data at the next address 2001 on the address data bus line 9. Option setting for a plurality of portions associated with the microcomputer is subsequently performed in a similar manner.
In the conventional option setting circuit of the above-described arrangement, however, since, during the program running period, the option setting is performed only at the time of resetting, if the option data latched by the option latch circuit is changed due to noise from external sources and electrostatic surge, the incorrect option is maintained until the next resetting. This results in a malfunction of the system.
Moreover, at the time of resetting during the program running period, since the latched option data is once reset to its initial state before being latched again, that is, since the option setting is changed, a malfunction may occur.